HT Re: [sldev] SL on Xeon processors

[Dzonatas]

Peter Phillips wrote:
> Dzonatas,
>
> Are you alluding to the use of hyper-threading?
http://news.zdnet.co.uk/hardware/0,1000000091,39286539,00.htm

The reason why current OS thread schedulers fail on HT systems are (1) 
dumb cache-awareness and (2)  paired threads that need to use the exact 
same resources that were not designed to be shared.

The methodology naturally follows more advanced software development skills.

http://en.wikipedia.org/wiki/Pair_programming

That wikipedia article starts to clearly state the idea, but it 
immediately went into some other issue about political discipline.

The architects of the BlueGene/L have loudly stated that two physically 
connected logical units are paired to do exactly two separate tasks. For 
example, one accesses the network bus while the other number crunches. 
In the BlueGene/L, there is 65,536 cores (two logical units per each 
CPU). The machine does about 280 teraflops.

http://www.llnl.gov/asc/computing_resources/bluegenel/

This is by no means meant to compare people who sit near each other in 
cubical style as an enabled HT multi-core processor.

Instead, Intel's 80x86 Terascale CPU has 80 of the x86 based processors. 
It is rated around 1.8 teraflops for a single CPU. That is 80 logical 
units per CPU.

If one replaced all the BlueGene/L CPUs with  80x86 Terascale CPUs, that 
would be about 117,964  teraflops. We can expect something like that 
performance increase in the next major supercomputer.

I allude the size of the 80x86 Terascale CPU to roughly the size of the 
CPU that is currently in a typical workstation. It uses about the same 
amount of power. The Xeon and others... similar size.

Intel's Nahelem, being partially derived from the terascale technology, 
is only the "tock" of the particular microarchitecture series.

For SL, the "tick" after would be the realization of a filled in void.

=)

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